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copyright aero?ex gaisler ab february 2013, issue 2.0 dual-core leon3-ft sparc v8 processor GR712RC data sheet gaisler descriptionthe GR712RC is an implementation of the dual-core leon3ft sparc v8 processor using radsafe tm technology. the fault tolerant design of the processor in combination with theradiation tolerant technology provides total immunity to radiation effects. speci?cation ? cqfp240 package ? total ionizing dose (tid) up to 300 krad(si) ? proven single-event latch-up (sel) immunity ? proven single-event upset (seu) tolerance ? 1.8v & 3.3v supply ? 15 mw/mhz processor core power consumption ? 100 mhz system frequency ? 200 mbps spacewire links ? 10 mbps ccsds telecommand link ? 50 mbps ccsds telemetry link features ? dual-core sparc v8 integer unit, each with 7-stage pipeline, 8 register windows, 4x4 kib multi- way instruction cache, 4x4 kib multi-way data cache, branch prediction, hardware multiplier and divider, power-down mode, hardware watchpoints, single- vector trapping, sparc reference memory management unit, etc. ? two high-performance double precision ieee-754 ?oating point units ? edac protected (8-bit bch and 16-bit reed- solomon) interface to multiple 8/32-bits prom/sram/sdram memory banks ? advanced on-chip debug support unit ? 192 kib edac protected on-chip memory ? multiple spacewire links with rmap target ? redundant 1553 bc/rt/mt interfaces ? redundant can 2.0 interfaces ? 10/100 ethernet mac with rmii interface ? spi, i 2 c, ascs16 (str), slink interfaces ? ccsds/ecss telemetry and telecommand ? uarts, timers & watchdog, gpio ports, interrupt controllers, status registers, jtag, etc. ? con?gurable i/o switch matrix applications GR712RC is an advanced system-on-chip, targeting high reliability rad-hard space, aeronautics and military applications. it incorporates a dual-core leon3-ft sparc v8 processor and is implemented using ramon chips radsafe tm library on tower semiconductors standard 180 nm cmos technology.
aeroflex gaisler 2 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table of contents 1 introduction.............................................................................................................................. 3 1.1 overview ................................................................................................................................................. 3 1.2 key features............................................................................................................................................. 3 1.3 signal overview ....................................................................................................................................... 5 1.4 signal description .................................................................................................................................... 6 1.5 i/o switch matrix overview ..................................................................................................................... 7 2 electrical characteristics ........................................................................................................ 18 2.1 absolute maximum ratings ................................................................................................................... 18 2.2 recommended operating conditions ..................................................................................................... 18 2.3 dc electrical performance characteristics............................................................................................. 19 2.4 ac electrical performance characteristics............................................................................................. 21 3 mechanical description .......................................................................................................... 37 3.1 package.................................................................................................................................................. 37 3.2 pin assignment....................................................................................................................................... 37 3.3 mechanical package drawings............................................................................................................... 43 4 reference documents ............................................................................................................. 45 5 screening, quali?cation, and quality control ......................................................................... 46 6 ordering information ............................................................................................................. 46 7 change record ........................................................................................................................ 47
aeroflex gaisler 3 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 1 introduction 1.1 overview GR712RC is a dual-core leon3-ft sparc v8 processor, with advanced interface protocols, dedi- cated for high reliability rad-hard aerospace applications. the GR712RC is fabricated at tower semiconductors ltd., using standard 180 nm cmos technol- ogy. it employs radiation-hard-by-design methods from aero?ex gaisler and the radsafe tm technol- ogy from ramon chips ltd., enabling superior radiation hardness together with excellent low-power performance. the leon3-ft processors provide hardware support for cache coherency, processor enumeration and interrupt steering. each processor core includes a sparc reference memory management unit (srmmu) and an ieee-754 compliant double-precision fpu for ?oating-point operations. it can be utilized in symmetric or asymmetric multiprocessing mode. the GR712RC architecture is centered around the amba advanced high-speed bus (ahb), to which the two leon3-ft processors and other high-bandwidth units are connected. low-bandwidth units are connected to the amba advanced peripheral bus (apb) which is accessed through an ahb to apb bridge. GR712RC is provided in a 240-pin, 0.5 mm pitch high-reliability ceramic quad ?at package (cqfp). this document is complemented by the GR712RC dual-core leon3-ft sparc v8 processor - user's manual from aero?ex gaisler [um], which provides information related to software integra- tion and development. 1.2 key features ? technology: 180 nm standard cmos, tower semiconductors ltd. ? library: 180 nm radsafe?, ramon chips ltd. ? package: ? 240 pin cqfp, 0.5 mm pitch, 32 mm * 32 mm, hermetically sealed, delivered with ?at pins and insulating lead-frame for customer trim and fold ? core voltage 1.8v +/- 0.15v, i/o voltage 3.3v +/- 0.3v ? -55oc to +125oc temperature range ? radiation tolerance: ? tid: 300 krad (si) ? sel: > 118 mev-cm 2 /mg ? seu: proven tolerance with hardened ?ip-?ops and error correction on all on-chip memories ? error detection and correction on external memories ? maximum system clock frequency of 100 mhz (depending on external memory choice) ? optional 2x internal system frequency multiplication by an all-digital dll ? optional 2x or 4x internal spacewire frequency multiplication by an all-digital dll ? clock-gating for each major core
aeroflex gaisler 4 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 ? two leon3-ft sparc v8 compliant 32-bit processors, each with: ? sparc reference memory management unit (srmmu) with 32 tlb entries ? high-performance double-precision ieee-754 ?oating point co-processor (grfpu) ? 16 kib multi-way instruction cache and 16 kib multi-way data cache ? internal on-chip high speed amba (ahb) bus ? instruction trace and amba (ahb) trace buffers for debugging ? timer unit with four 32-bit timers including watchdog ? secondary timer unit with four 32-bit timers ? primary and secondary interrupt controller for 31 interrupts ? on-chip 192 kib memory block with edac ? external memory support: ? bus width: 8 bits, or 32 bit data plus 8/16 bits for edac checkbits, 24 bit address ? 8 bit bch edac for sram and prom, 16 bit reed-solomon edac for sdram ? memory types: sram, sdram, prom / eeprom / nor-flash and i/o address space ? programmable wait-states: ? sram read/write cycle 2 - 5 clock cycles ? prom / eeprom / nor-flash read cycle 2 - 32 clock periods ? one idle clock period between accesses to sram and prom ? debug support unit (dsu) accessed via jtag and spacewire rmap targets ? two spacewire ports with rmap targets, maximum 200 mbps full-duplex data rate ? con?gurable i/o selection matrix, connecting a subset of available i/o units to 67 shared pins: ? four spacewire ports, maximum 200 mbps full-duplex data rate ? redundant mil-std-1553b brm (bc/rt/bm) interface ? two can 2.0b bus controllers ? six uart ports, with 8-byte fifo ? ethernet mac with rmii 10/100 mbps port ? spi master serial port ? i2c master serial port ? ascs16 (str) serial port ? slink 6 mhz serial port ? ccsds / ecss telecommand decoder (?ve input channels), maximum 10 mbps input rate ? ccsds / ecss telemetry encoder, maximum 50 mbps output rate ? 26 input and 38 input/output general purpose ports
aeroflex gaisler 5 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 1.3 signal overview figure 1. signal overview dllbpn address[23:0] data[31:0] cb[7:0] ramsn[1:0] ramoen ramwen romsn[1:0] iosn oen read writen brdyn bexcn inclkresetn errorn wdogn spwclk spw_rxd[1:0] spw_rxs[1:0] spw_txd[1:0] spw_txs[1:0] memory interface spacewire links clock & reset error & watchdog tcktms tdi tdo jtag sdclk swmx[66:0] i/o matrix testen scanen test
aeroflex gaisler 6 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 1.4 signal description the external signals are described in table 1. table 1. external signals name usage direction polarity inclk main system clock in - dllbpn dll bypass in low resetn system reset in low scanen scan enable (tie to ground) in high testen test enable (tie to ground) in high errorn processor error mode out-tri low wdogn watchdog output out-tri low tck jtag test clock in - tms jtag test mode in high tdi jtag test data input in - tdo jtag test data output out - address[23:0] memory address out - data[31:0] memory data bus in/out - cb[7:0] memory checkbits in/out - ramsn[1:0] sram chip selects out low ramoen sram output enable out low ramwen sram write enable strobe out low oen prom, i/o output enable out low writen prom, i/o write strobe out low read sram, prom i/o read indicator 1) out high iosn i/o area chip select out low romsn[1:0] prom chip selects out low brdyn bus ready in low bexcn bus exception in low sdclk sdram clock out - spwclk spacewire receiver and transmitter clock in - spw_rxd[1:0] spacewire data input in high spw_rxs[1:0] spacewire strobe input in high spw_txd[1:0] spacewire data output out high spw_txs[1:0] spacewire strobe output out high swmx[66:0] i/o switch matrix in/out - note 1: the read signal may also change value during sdram accesses.
aeroflex gaisler 7 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 1.5 i/o switch matrix overview the i/o switch matrix provides access to several i/o units. when an interface is not activated, its pins automatically become general purpose i/o. after reset, all i/o switch matrix pins are de?ned as i/o until programmed otherwise. note that some pins are input only, some are output only, and the rest are both input and output, as described in table 3. the enabling of the i/o units is described in [um]. figure 2 shows how the various i/o units are connected to the i/o switch matrix. table 2 shows examples of possible con?gurations using the i/o switch matrix. note that two spacewire interfaces are always available outside the i/o switch matrix. table 3 shows a listing of all pins in the i/o switch matrix, indicating the priority amongst them. table 4 shows a listing of pin utilization per i/o unit. table 5 shows a listing of pins in the i/o switch matrix grouped per function (gpio is not listed). table 6 shows a complete listing of con?icts between i/o units (gpio is not listed). table 2. example of possible con?gurations using the i/o switch matrix. note that other con?gurations are also possible. interface type example con?guration cf0 cf1 cf2 cf3 cf4 cf5 sdram with or without reed-solomon 1 1 1 1 1 uart 6 4 6 6 6 6 spacewire 6 4 2 2 4 3 ethernet 1 1 mil-std-1553b bc/rt/bm 1 i2c 1 1 1 1 1 spi 1 1 1 slink 1 1 ascs16 1 ccsds/ecss tc & tm 1 figure 2. architectural block diagram showing connections to the i/o switch matrix can tm i2c spi ascs gpio gpio timers irq sdram tc mctrl 1553 eth slink jtag dsu spw spw spw spw spw spw stat uart uart uart uart uart uart 192k ram canmux gpreg clkgate leon3ft leon3ft amba errorn wdogn tms, tck inclk, spwclk address[23:0] swmx[66:0] spw_txd/s[1:0]spw_rxd/s[1:0] data[31:0], cb[7:0] ctrl, sdclk dllbpn, resetn testenscanen tdi, tdo
aeroflex gaisler 8 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 3. i/o switch matrix pin description, de?ning the order of priority for outputs and input/outputs, with the highestpriority for each pin listed ?rst. pin no. pin name pin function polarity reset value dir. description 4 swmx[0] uart_tx[0] - high out uart transmit 0 3 swmx[1] uart_rx[0] - in uart receive 0 2 swmx[2] uart_tx[1] - high out uart transmit 1 1 swmx[3] uart_rx[1] - in uart receive 1 gpio[0] - in gpio 1 register, bit 0 (input only) 240 swmx[4] uart_tx[2] - high-z out uart transmit 2 gpio[1] - high-z in/out gpio 1 register, bit 1 mcfg3[8] - in at reset, bit 8 in mcfg3 register in the mem- ory controller is set from this input. 239 swmx[5] uart_rx[2] - in uart receive 2 gpio[2] - in gpio 1 register, bit 2 (input only) 238 swmx[6] uart_tx[3] - high-z out uart transmit 3 gpio[3] - high-z in/out gpio 1 register, bit 3 mcfg1[9] - in at reset, bit 9 in mcfg1 register in the mem- ory controller is set from this input 233 swmx[7] uart_rx[3] - in uart receive 3 gpio[4] - in gpio 1 register, bit 4 (input only) 232 swmx[8] uart_tx[4] - high-z out uart transmit 4 tmdo - high-z out telemetry data out gpio[5] - high-z in/out gpio 1 register, bit 5 231 swmx[9] uart_rx[4] - in uart receive 4 tmclki rising in telemetry clock input gpio[6] - in gpio 1 register, bit 6 (input only) 230 swmx[10] uart_tx[5] - high-z out uart transmit 5 tmclko - high-z out telemetry clock output gpio[7] - high-z in/out gpio 1 register, bit 7 229 swmx[11] uart_rx[5] - in uart receive 5 tcact[0] high in telecommand active 0 gpio[8] - in gpio 1 register, bit 8 (input only) 228 swmx[12] spw_txs[4] high high-z out spacewire transmit strobe 4 sdcsn[0] low high-z out sdram select 0 gpio[9] - high-z in/out gpio 1 register, bit 9 227 swmx[13] spw_txd[4] high high-z out spacewire transmit data 4 sdcsn[1] low high-z out sdram select 1 gpio[10] - high-z in/out gpio 1 register, bit 10 226 swmx[14] spw_rxs[4] high in spacewire receive strobe 4 tcclk[0] rising in telecommand clock 0 a16dasa - in ascs das a - slave data in gpio[11] - in gpio 1 register, bit 11 (input only) 225 swmx[15] spw_rxd[4] high in spacewire receive data 4 tcd[0] - in telecommand data 0 a16dasb - in ascs das b - slave data in gpio[12] - in gpio 1 register, bit 12 (input only) 220 swmx[16] spw_txs[2] high high-z out spacewire transmit strobe 2 cantxa - high-z out can transmit a gpio[13] - high-z in/out gpio 1 register, bit 13
aeroflex gaisler 9 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 219 swmx[17] spw_txd[2] high high-z out spacewire transmit data 2 cantxb - high-z out can transmit b gpio[14] - high-z in/out gpio 1 register, bit 14 218 swmx[18] spw_rxs[2] high in spacewire receive strobe 2 canrxa - in can receive a gpio[15] - in gpio 1 register, bit 15 (input only) 217 swmx[19] spw_rxd[2] high in spacewire receive data 2 canrxb - in can receive b gpio[16] - in gpio 1 register, bit 16 (input only) 203 swmx[20] spw_txs[3] high high-z out spacewire transmit strobe 3 slsync high high-z out slink sync gpio[17] - high-z in/out gpio 1 register, bit 17 202 swmx[21] spw_txd[3] high high-z out spacewire transmit data 3 a16etr high high-z out ascs etr - synchronization signal gpio[18] - high-z in/out gpio 1 register, bit 18 201 swmx[22] spw_rxs[3]] high in spacewire receive strobe 3 gpio[19] - in gpio 1 register, bit 19 (input only) 200 swmx[23] spw_rxd[3] high in spacewire receive data 3 gpio[20] - in gpio 1 register, bit 20 (input only) 197 swmx[24] spw_txd[5] high high-z out spacewire transmit data 5 sddqm[0] high high-z out sdram data mask 0, corresponds to data[7:0] gpio[21] - high-z in/out gpio 1 register, bit 21 196 swmx[25] spw_txs[5] high high-z out spacewire transmit strobe 5 sddqm[1] high high-z out sdram data mask 1, corresponds to data[15:8] gpio[22] - high-z in/out gpio 1 register, bit 22 193 swmx[26] spw_rxs[5] high in spacewire receive strobe 5 tcrfavl[0] high in telecommand rf available 0 gpio[23] - in gpio 1 register, bit 23 (input only) 192 swmx[27] spw_rxd[5] high in spacewire receive data 5 tcclk[1] rising in telecommand clock 1 gpio[24] - in gpio 1 register, bit 24 (input only) 191 swmx[28] 1553rxena high high-z out mil-std-1553b receive enable a - high-z out proprietary, enabled by can rmtxd[0] - high-z out ethernet transmit data 0 gpio[25] - high-z in/out gpio 1 register, bit 25 190 swmx[29] 1553txa high high-z out mil-std-1553b transmit positive a - high-z out proprietary, enabled by can rmtxd[1] - high-z out ethernet transmit data 1 gpio[26] - high-z in/out gpio 1 register, bit 26 189 swmx[30] 1553rxa high in mil-std-1553b receive positive a tcd[1] - in telecommand data 1 rmrxd[0] - in ethernet receive data 0 gpio[27] - in gpio 1 register, bit 27 (input only) table 3. i/o switch matrix pin description, de?ning the order of priority for outputs and input/outputs, with the highestpriority for each pin listed ?rst. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 10 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 188 swmx[31] 1553rxna low in mil-std-1553b receive negative a tcact[1] high in telecommand active 1 rmrxd[1] - in ethernet receive data 1 gpio[28] - in gpio 1 register, bit 28 (input only) 185 swmx[32] 1553txna low high-z out mil-std-1553b transmit negative a - high-z out proprietary, enabled by can rmtxen high high-z out ethernet transmit enable gpio[29] - high-z in/out gpio 1 register, bit 29 184 swmx[33] 1553txinha high high-z out mil-std-1553b transmit inhibit a - high-z out proprietary, enabled by can gpio[30] - high-z in/out gpio 1 register, bit 30 183 swmx[34] 1553rxb high in mil-std-1553b receive positive b tcrfavl[1] high in telecommand rf available 1 rmcrsdv high in ethernet carrier sense / data valid gpio[31] - in gpio 1 register, bit 31 (input only) 182 swmx[35] 1553rxnb low in mil-std-1553b receive negative b tcclk[2] rising in telecommand clock 2 rmintn low in ethernet management interrupt gpio[32] - in gpio 2 register, bit 0 (input only) 179 swmx[36] 1553rxenb high high-z out mil-std-1553b receive enable b a16mcs high high-z out ascs mcs - tm start/stop signal rmmdio - high-z in/out ethernet media interface data gpio[33] - high-z in/out gpio 2 register, bit 1 178 swmx[37] 1553txb high high-z out mil-std-1553b transmit positive b a16hs high high-z out ascs hs - tm/tc serial clock rmmdc - high-z out ethernet media interface clock gpio[34] - high-z in/out gpio 2 register, bit 2 spacewire clock divisor registers - in at reset, bits 8 and 0 in the clock divisor reg- ister of the spacewire interfaces are set from this input 177 swmx[38] 1553ck - in mil-std-1553b clock tcd[2] - in telecommand data 2 rmrfclk - in ethernet reference clock gpio[35] - in gpio 2 register, bit 3 (input only) 176 swmx[39] tcact[2] high in telecommand active 2 gpio[36] - in gpio 2 register, bit 4 (input only) 175 swmx[40] 1553txnb low high-z out mil-std-1553b transmit negative b a16dcs - high-z out ascs dcs - slave data out gpio[37] - high-z in/out gpio 2 register, bit 5 spacewire clock divisor registers - in at reset, bits 9 and 1 in the clock divisor reg- ister of the spacewire interfaces are set from this input 174 swmx[41] 1553txinhb high high-z out mil-std-1553b transmit inhibit b a16mas high high-z out ascs mas - tm start/stop signal gpio[38] - high-z in/out gpio 2 register, bit 6 table 3. i/o switch matrix pin description, de?ning the order of priority for outputs and input/outputs, with the highestpriority for each pin listed ?rst. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 11 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 173 swmx[42] tcrfavl[2] high in telecommand rf available 2 gpio[39] - in gpio 2 register, bit 7 (input only) 172 swmx[43] - high-z out proprietary, enabled by can gpio[40] - high-z in/out gpio 2 register, bit 8 spacewire clock divisor registers - in at reset, bits 10 and 2 in the clock divisor reg- ister of the spacewire interfaces are set from this input 169 swmx[44] spiclk high-z out spi clock slo - high-z out slink data out gpio[41] - high-z in/out gpio 2 register, bit 9 166 swmx[45] spimosi - high-z out spi master out slave in slclk high high-z out slink clock gpio[42] - high-z in/out gpio 2 register, bit 10 spacewire clock divisor registers - in at reset, bits 11 and 3 in the clock divisor reg- ister of the spacewire interfaces are set from this input 165 swmx[46] tcclk[3] rising in telecommand clock 3 gpio[43] - in gpio 2 register, bit 11 (input only) 164 swmx[47] tcd[3] - in telecommand data 3 gpio[44] - in gpio 2 register, bit 12 (input only) 163 swmx[48] sdcasn low high-z out sdram column address strobe gpio[45] - high-z in/out gpio 2 register, bit 13 162 swmx[49] sdrasn low high-z out sdram row address strobe gpio[46] - high-z in/out gpio 2 register, bit 14 161 swmx[50] tcact[3] high in telecommand active 3 gpio[47] - in gpio 2 register, bit 15 (input only) 160 swmx[51] spimiso in spi master in slave out tcrfavl[3] high in telecommand rf available 3 sli - in slink data in gpio[48] - in gpio 2 register, bit 16 (input only) 157 swmx[52] sdwen low high-z out sdram write enable gpio[49] - high-z in/out gpio 2 register, bit 17 155 swmx[53] sddqm[2] high high-z out sdram data mask 2, corresponds to data[23:16] gpio[50] - high-z in/out gpio 2 register, bit 18 154 swmx[54] sddqm[3] high high-z out sdram data mask 3, corresponds to data[31:24] gpio[51] - high-z in/out gpio 2 register, bit 19 153 swmx[55] tcact[4] high in telecommand active 4 gpio[52] - in gpio 2 register, bit 20 (input only) 144 swmx[56] tcrfavl[4] high in telecommand rf available 4 gpio[53] - in gpio 2 register, bit 21 (input only) 143 swmx[57] i2csda high-z in/out i2c serial data gpio[54] - high-z in/out gpio 2 register, bit 22 tcclk[4] rising in telecommand clock 4 142 swmx[58] i2cscl high-z in/out i2c serial clock gpio[55] - high-z in/out gpio 2 register, bit 23 tcd[4] - in telecommand data 4 table 3. i/o switch matrix pin description, de?ning the order of priority for outputs and input/outputs, with the highestpriority for each pin listed ?rst. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 12 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 140 swmx[59] cb[8] - high-z in/out reed-solomon check bit 8 gpio[56] - high-z in/out gpio 2 register, bit 24 137 swmx[60] cb[9] - high-z in/out reed-solomon check bit 9 gpio[57] - high-z in/out gpio 2 register, bit 25 136 swmx[61] cb[10] - high-z in/out reed-solomon check bit 10 gpio[58] - high-z in/out gpio 2 register, bit 26 135 swmx[62] cb[11] - high-z in/out reed-solomon check bit 11 gpio[59] - high-z in/out gpio 2 register, bit 27 132 swmx[63] cb[12] - high-z in/out reed-solomon check bit 12 gpio[60] - high-z in/out gpio 2 register, bit 28 129 swmx[64] cb[13] - high-z in/out reed-solomon check bit 13 gpio[61] - high-z in/out gpio 2 register, bit 29 128 swmx[65] cb[14] - high-z in/out reed-solomon check bit 14 gpio[62] - high-z in/out gpio 2 register, bit 30 127 swmx[66] cb[15] - high-z in/out reed-solomon check bit 15 gpio[63] - high-z in/out gpio 2 register, bit 31 table 3. i/o switch matrix pin description, de?ning the order of priority for outputs and input/outputs, with the highestpriority for each pin listed ?rst. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 13 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 4. i/o switch matrix pin utilization per interface type interface type pin function direction total in out in/out sdram sddqm[3:0], sdcasn, sdrasn, sdwen, sdcsn[1:0] 9 9 sdram reed-solomon cb[15:8] 8 8 gpio gpio[...] 26 38 64 uart uart_tx[5:0], uart_rx[5:0] 6 6 12 spacewire spw_rxd[5:2], spw_rxs[5:2], spw_txd[5:2], spw_txs[5:2] 8 8 16 ethernet rmtxd[1:0], rmtxen, rmmdio, rmmdc 5 4 1 10 rmrfclk, rmrxd[0:1], rmcrsdv, rmintn can cantxa, canrxa, cantxb, canrxb 4 4 8 mil-std-1553b bc/rt/bm 1553rxa, 1553rxna, 1553rxena, 1553txa, 1553txna, 1553txinha 5 8 13 1553rxb, 1553rxnb, 1553rxenb, 1553txb, 1553txnb, 1553txinhb1553ck i2c i2csda, i2cscl 2 2 spi spiclk, spimosi, spimiso 1 2 3 slink sli, slo, slsync, slclk 1 3 4 ascs16 a16dasa, a16dasb, a16mcs, a16hs, a16dcs, a16mas, a16etr 2 5 7 ccsds/ecss tc tcact[4:0], tcd[4:0], tcclk[4:0], tcrfav[4:0] 20 20 ccsds/ecss tm tmdo, tmclko, tmclki 1 2 3
aeroflex gaisler 14 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 5. i/o switch matrix pins listed per function, including supporting signals outside the i/o switch matrix. pin no. pin name pin function polarity reset value dir. description 157 swmx[52] sdwen low high-z out sdram write enable 163 swmx[48] sdcasn low high-z out sdram column address strobe 162 swmx[49] sdrasn low high-z out sdram row address strobe 228 swmx[12] sdcsn[0] low high-z out sdram select 0 227 swmx[13] sdcsn[1] low high-z out sdram select 1 197 swmx[24] sddqm[0] high high-z out sdram data mask 0, corresponds to data[7:0] 196 swmx[25] sddqm[1] high high-z out sdram data mask 1, corresponds to data[15:8] 155 swmx[53] sddqm[2] high high-z out sdram data mask 2, corresponds to data[23:16] 154 swmx[54] sddqm[3] high high-z out sdram data mask 3, corresponds to data[31:24] 140 swmx[59] cb[8] - high-z in/out check bit 8, reed-solomon 137 swmx[60] cb[9] - high-z in/out check bit 9, reed-solomon 136 swmx[61] cb[10] - high-z in/out check bit 10, reed-solomon 135 swmx[62] cb[11] - high-z in/out check bit 11, reed-solomon 132 swmx[63] cb[12] - high-z in/out check bit 12, reed-solomon 129 swmx[64] cb[13] - high-z in/out check bit 13, reed-solomon 128 swmx[65] cb[14] - high-z in/out check bit 14, reed-solomon 127 swmx[66] cb[15] - high-z in/out check bit 15, reed-solomon address[16:2] address[16:2] - low out memory address data[31:0] data[31:0] - high-z in/out memory data bus cb[7:0] cb[7:0] - high-z in/out memory checkbits 240 swmx[4] mcfg3[8] - in at reset, bit 8 in mcfg3 register in the memory controller is set from this input. 238 swmx[6] mcfg1[9] - in at reset, bit 9 in mcfg1 register in the memory controller is set from this input 4 swmx[0] uart_tx[0] - high out uart transmit 0 3 swmx[1] uart_rx[0] - in uart receive 0 2 swmx[2] uart_tx[1] - high out uart transmit 1 1 swmx[3] uart_rx[1] - in uart receive 1 240 swmx[4] uart_tx[2] - high-z out uart transmit 2 239 swmx[5] uart_rx[2] - in uart receive 2 238 swmx[6] uart_tx[3] - high-z out uart transmit 3 233 swmx[7] uart_rx[3] - in uart receive 3 232 swmx[8] uart_tx[4] - high-z out uart transmit 4 231 swmx[9] uart_rx[4] - in uart receive 4 230 swmx[10] uart_tx[5] - high-z out uart transmit 5 229 swmx[11] uart_rx[5] - in uart receive 5 213 spw_rxd[0] spw_rxd[0] high in spacewire receive data 0 214 spw_rxs[0] spw_rxs[0] high in spacewire receive strobe 0 215 spw_txd[0] spw_txd[0] high low out spacewire transmit data 0 216 spw_txs[0] spw_txs[0] high low out spacewire transmit strobe 0 204 spw_rxd[1] spw_rxd[1] high in spacewire receive data 1 205 spw_rxs[1] spw_rxs[1] high in spacewire receive strobe 1 206 spw_txd[1] spw_txd[1] high low out spacewire transmit data 1 209 spw_txs[1] spw_txs[1] high low out spacewire transmit strobe 1 217 swmx[19] spw_rxd[2] high in spacewire receive data 2
aeroflex gaisler 15 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 218 swmx[18] spw_rxs[2] high in spacewire receive strobe 2 219 swmx[17] spw_txd[2] high high-z out spacewire transmit data 2 220 swmx[16] spw_txs[2] high high-z out spacewire transmit strobe 2 200 swmx[23] spw_rxd[3] high in spacewire receive data 3 201 swmx[22] spw_rxs[3] high in spacewire receive strobe 3 202 swmx[21] spw_txd[3] high high-z out spacewire transmit data 3 203 swmx[20] spw_txs[3] high high-z out spacewire transmit strobe 3 225 swmx[15] spw_rxd[4] high in spacewire receive data 4 226 swmx[14] spw_rxs[4] high in spacewire receive strobe 4 227 swmx[13] spw_txd[4] high high-z out spacewire transmit data 4 228 swmx[12] spw_txs[4] high high-z out spacewire transmit strobe 4 192 swmx[27] spw_rxd[5] high in spacewire receive data 5 193 swmx[26] spw_rxs[5] high in spacewire receive strobe 5 197 swmx[24] spw_txd[5] high high-z out spacewire transmit data 5 196 swmx[25] spw_txs[5] high high-z out spacewire transmit strobe 5 178 swmx[37] spacewire clock divisor registers values at reset, all other bits are zero. - in at reset, bits 8 & 0 are set from this input 175 swmx[40] - in at reset, bits 9 & 1 are set from this input 172 swmx[43] - in at reset, bits 10 & 2 are set from this input 166 swmx[45] - in at reset, bits 11 & 3 are set from this input 185 swmx[32] rmtxen high high-z out ethernet transmit enable 191 swmx[28] rmtxd[0] - high-z out ethernet transmit data 0 190 swmx[29] rmtxd[1] - high-z out ethernet transmit data 1 189 swmx[30] rmrxd[0] - in ethernet receive data 0 188 swmx[31] rmrxd[1] - in ethernet receive data 1 183 swmx[34] rmcrsdv high in ethernet carrier sense / data valid 182 swmx[35] rmintn low in ethernet management interrupt 179 swmx[36] rmmdio - high-z in/out ethernet media interface data 178 swmx[37] rmmdc - high-z out ethernet media interface clock 177 swmx[38] rmrfclk - in ethernet reference clock 220 swmx[16] cantxa - high-z out can transmit a 218 swmx[18] canrxa - in can receive a 219 swmx[17] cantxb - high-z out can transmit b 217 swmx[19] canrxb - in can receive b 191 swmx[28] - high-z out proprietary, enabled by can 190 swmx[29] - high-z out proprietary, enabled by can 185 swmx[32] - high-z out proprietary, enabled by can 184 swmx[33] - high-z out proprietary, enabled by can 172 swmx[43] - high-z out proprietary, enabled by can 177 swmx[38] 1553ck - in mil-std-1553b clock 184 swmx[33] 1553txinha high high-z out mil-std-1553b transmit inhibit a 190 swmx[29] 1553txa high high-z out mil-std-1553b transmit positive a 185 swmx[32] 1553txna low high-z out mil-std-1553b transmit negative a 191 swmx[28] 1553rxena high high-z out mil-std-1553b receive enable a 189 swmx[30] 1553rxa high in mil-std-1553b receive positive a 188 swmx[31] 1553rxna low in mil-std-1553b receive negative a 174 swmx[41] 1553txinhb high high-z out mil-std-1553b transmit inhibit b 178 swmx[37] 1553txb high high-z out mil-std-1553b transmit positive b table 5. i/o switch matrix pins listed per function, including supporting signals outside the i/o switch matrix. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 16 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 175 swmx[40] 1553txnb low high-z out mil-std-1553b transmit negative b 179 swmx[36] 1553rxenb high high-z out mil-std-1553b receive enable b 183 swmx[34] 1553rxb high in mil-std-1553b receive positive b 182 swmx[35] 1553rxnb low in mil-std-1553b receive negative b 143 swmx[57] i2csda high-z in/out i2c serial data 142 swmx[58] i2cscl high-z in/out i2c serial clock 169 swmx[44] spiclk high-z out spi clock 166 swmx[45] spimosi - high-z out spi master out slave in 160 swmx[51] spimiso in spi master in slave out 203 swmx[20] slsync high high-z out slink sync 166 swmx[45] slclk high high-z out slink clock 160 swmx[51] sli - in slink data in 169 swmx[44] slo - high-z out slink data out 226 swmx[14] a16dasa - in ascs das a - slave data in 225 swmx[15] a16dasb - in ascs das b - slave data in 202 swmx[21] a16etr high high-z out ascs etr - synchronization signal 175 swmx[40] a16dcs - high-z out ascs dcs - slave data out 174 swmx[41] a16mas high high-z out ascs mas - tm start/stop signal 179 swmx[36] a16mcs high high-z out ascs mcs - tc start/stop signal 178 swmx[37] a16hs high high-z out ascs hs - tm/tc serial clock 229 swmx[11] tcact[0] high in telecommand active 0 226 swmx[14] tcclk[0] rising in telecommand clock 0 225 swmx[15] tcd[0] - in telecommand data 0 193 swmx[26] tcrfavl[0] high in telecommand rf available 0 188 swmx[31] tcact[1] high in telecommand active 1 192 swmx[27] tcclk[1] rising in telecommand clock 1 189 swmx[30] tcd[1] - in telecommand data 1 183 swmx[34] tcrfavl[1] high in telecommand rf available 1 176 swmx[39] tcact[2] high in telecommand active 2 182 swmx[35] tcclk[2] rising in telecommand clock 2 177 swmx[38] tcd[2] - in telecommand data 2 173 swmx[42] tcrfavl[2] high in telecommand rf available 2 161 swmx[50] tcact[3] high in telecommand active 3 165 swmx[46] tcclk[3] rising in telecommand clock 3 164 swmx[47] tcd[3] - in telecommand data 3 160 swmx[51] tcrfavl[3] high in telecommand rf available 3 153 swmx[55] tcact[4] high in telecommand active 4 143 swmx[57] tcclk[4] rising in telecommand clock 4 142 swmx[58] tcd[4] - in telecommand data 4 144 swmx[56] tcrfavl[4] high in telecommand rf available 4 231 swmx[9] tmclki rising in telemetry clock input 230 swmx[10] tmclko - high-z out telemetry clock output 232 swmx[8] tmdo - high-z out telemetry data out table 5. i/o switch matrix pins listed per function, including supporting signals outside the i/o switch matrix. pin no. pin name pin function polarity reset value dir. description
aeroflex gaisler 17 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 6. con?icting interfaces in the i/o switch matrix are marked with an x, with duplicates shown in bold typeface. sdram (with rs) - x x uart 0 - uart 1 - uart 2 - uart 3 - uart 4 - x uart 5 - x x spacewire 0 - spacewire 1 - spacewire 2 - x x spacewire 3 - x spacewire 4 x - x x spacewire 5 x - x x ethernet - x x x x can x x - mil-std-1553b x - x x x i2c - x spi - x x slink x x - x ascs x x x - x ccsds tc 0 x x x x - ccsds tc 1 x x x - ccsds tc 2 x x - ccsds tc 3 x x - ccsds tc 4 x - ccsds tm x x - sdram (with rs) uart 0 uart 1 uart 2 uart 3 uart 4 uart 5 spacewire 0 spacewire 1 spacewire 2 spacewire 3 spacewire 4 spacewire 5 ethernet can mil-std-1553b i2c spi slink ascs ccsds tc 0 ccsds tc 1 ccsds tc 2 ccsds tc 3 ccsds tc 4 ccsds tm
aeroflex gaisler 18 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2 electrical characteristics 2.1 absolute maximum ratings these values specify the stress that might apply to the device without causing it permanent damage. 2.2 recommended operating conditions table 7. absolute maximum ratings 1) symbol parameter rating units min. max. v ddio dc supply voltage for i/o -0.3 4.2 v v dd dc supply voltage for core -0.3 2.4 v v in input voltage -0.3 v ddio + 0.3 v t stor storage temperature -65 +150 ?c t case operating case temperature -55 +125 ?c t solder lead temperature (soldering 10 sec.) +250 ?c t j junction temperature +150 ?c q jc (ceramic) thermal resistance, junction to case 4 ?c/w p d power dissipation 6.25 w note 1: extended operation at the maximum levels may degrade the performance and affect the reliability of the device. table 8. recommended operating conditions symbol parameter rating units min. typ. max. v ddio dc supply voltage for i/o 3.0 3.3 3.6 v v dd dc supply voltage for core 1.65 1.8 1.95 v v in input voltage 0 v ddio v t case operating case temperature -55 +125 ?c sl in slew rate of all inputs 1) 0.4 v/ns note 1: applies only to the range 0.8 v and 2.0 v.
aeroflex gaisler 19 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.3 dc electrical performance characteristics table 9. dc characteristics (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) symbol parameter condition rating units min. typ. max. v oh output high voltage 1) i oh = -4 ma 2) i oh = -6 ma 3) 2.4 v v ol output low voltage i ol = 4 ma 2) i ol = 6 ma 3) 0.5 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i ileak input leakage current -10 10 ua i oleak output leakage current outputs at tri-state -10 10 ua i os short-circuit output current v o = v ddio , v ddio = 3.6 v v o = 0 v, v ddio = 3.6 v -120 5) 120 5) ma i dds core static current f clk = 0 mhz 1 10 ma i dd core supply current f clk = 100 mhz 0.9 2.0 5) a i ddios i/o static current 4) f clk = 0 mhz v ddio = 3.6 v 0.2 2 ma i ddio i/o supply current 6) ma c i/o i/o pad capacitance 5) 15 pf note 1: except open-drain outputs errorn, wdogn, i2cscl and i2csda. note 2: all outputs de?ned with a maximum load of 50 pf. note 3: all outputs de?ned with a maximum load of 100 pf. note 4: all inputs at 0 v or v ddio . no resistive load. note 5: supplied as a design limit. parameter not measured during production test. note 6: the dynamic power consumption of the i/o supply can be calculated as a function of the average frequency and the capacitive load of each output i : sum of [f i/o * c load ] ( i ) * (v ddio ) 2
aeroflex gaisler 20 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 10. detailed core power consumption (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) test condition rating units typ. max. 1) static, no clocks or toggling signals 30 50 mw standby, all cores clock gated 4 6 mw/mhz 1 processor core active at 50%, remaining ip cores clock gated 7 10 mw/mhz 1 processor core active at 100%, remaining ip cores clock gated 10 15 mw/mhz 2 processor cores active at 100%, remaining ip cores clock gated 15 24 mw/mhz 1 spacewire link active @ 100 mbit/s 1 1.5 mw/mhz 2 can interfaces active 100% @ 1 mbit/s 1 1.5 mw/mhz telemetry encoder active @ 10 mbit/s 0.5 1 mw/mhz note 1: supplied as a design limit. parameter not measured during production test.
aeroflex gaisler 21 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4 ac electrical performance characteristics all measured ac parameters have been tested with a 50 pf - 70 pf capacitive load on the outputs. transition time measurements have been tested at a voltage level of 1.4 v. equivalent load chart is provided in the product speci?cation [ps.] 2.4.1 clock the timing waveforms and timing parameters are shown in ?gure 3 and are de?ned in table 11. table 11. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference min max unit t inclk input clock period without dll inclk 10 - ns f inclk input clock frequency without dll 2) inclk - 100 mhz t inclk_high input clock high phase without dll 5) inclk 4.5 ns t inclk_low input clock low phase without dll 5) inclk 4.5 ns t inclk input clock period with dll 1) inclk 20 22 3) ns f inclk input clock frequency with dll 1) 2) inclk 46 3) 50 mhz dc inclk input frequency duty cycle with dll inclk 35 65 % t inclk_high input clock high phase with dll 5) inclk 7 ns t inclk_low input clock low phase with dll 5) inclk 7 ns t clk internal system clock period 4) 5) 6) - 10 - ns f clk internal system clock frequency 2) 4) 5) 6) - - 100 mhz note 1: for the system clock, the dll provides a times 2 multiplication of the input frequency. note 2: t inclk = 1/f inclk, t clk = 1/f clk note 3: parameter not measured during production test. note 4: applies to the system clock only (i.e. processor and amba clock) only. spacewire clocks are dis- cussed in section 2.4.9. note 5: the maximum internal system clock frequency is speci?ed by the parameters t clk and f clk . the parameters t inclk and f inclk specify the what the clock input pin and the dll can support, and not what the internal logic can support. note 6: the internal system clock frequency is limited by the timing of the memory interface towards external synchronous memory components. figure 3. timing waveforms inclk t inclk
aeroflex gaisler 22 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.2 reset and initialization the timing waveforms and timing parameters are shown in ?gure 4 and are de?ned in table 12. 2.4.3 leon3 - high-performance sparc v8 32-bit processor the timing waveforms and timing parameters are shown in ?gure 5 and are de?ned in table 13. table 12. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t rstgen0 asserted period - 10 - t inclk periods note 1: the resetn input is re-synchronized internally. note 2: v dd must reach at least minimum operating voltage for t restgen0 before resetn is de-asserted. note 3: if dll is used, the internal reset is released 2048 t inclk periods after resetn is de-asserted note 4: after power-up all ?ip-?ops, on-chip memory and dll are in an unknown state before reset. table 13. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t leon0 clock to output delay rising inclk edge 2 1) 23 2) ns t leon1 clock to output tri-state rising inclk edge 50 1) ns note 1: parameter not measured during production test. note 2: parameter measured during production test without dll enabled. note 3: for correct operation, the signal should be pulled-up externally with 1- 10 kohm. GR712RC does not include any internal pull-up resistors. figure 4. timing waveforms resetn inclk t rstgen0 figure 5. timing waveforms t leon0 errorn inclk t leon1
aeroflex gaisler 23 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.4 fault tolerant memory controller the timing waveforms and timing parameters are shown in ?gure 6 and are de?ned in table 14. figure 6. timing waveforms - sram (0 wait state) access, prom (0 wait state) access t ftmctrl0 address[23:0] sdclk t ftmctrl1 data[31:0], cb[7:0] (output) data[31:0], cb[7:0] (input) ramsn[1:0] t ftmctrl3, t ftmctrl4 read ramwen, writen t ftmctrl9 brdyn, bexcn t ftmctrl10 t ftmctrl2 t ftmctrl2 t ftmctrl6 t ftmctrl6 address[23:0] sdclk ramsn[1:0] t ftmctrl7 t ftmctrl8 t ftmctrl5 t ftmctrl1 romsn[1:0] romsn[1:0] read t ftmctrl2 t ftmtrl2 ramoen, oen
aeroflex gaisler 24 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 the timing waveforms and timing parameters are shown in ?gure 7 and are de?ned in table 14. figure 7. timing waveforms - i/o accesses t ftmctrl0 address[23:0] sdclk t ftmctrl1 data[31:0] (output) data[31:0] (input) iosn t ftmctrl3, t ftmctrl4 oen ramwen, writen t ftmctrl9 brdyn, bexcn t ftmctrl10 t ftmctrl2 t ftmctrl2 t ftmctrl6 t ftmctrl6 address[23:0] sdclk iosn t ftmctrl7 t ftmctrl8 t ftmctrl5 t ftmctrl1 t ftmctrl2 t ftmctrl2 read read
aeroflex gaisler 25 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 14. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge 2) min max unit t ftmctrl0 address clock to output delay 3) rising sdclk edge 0 1) 7.5 ns t ftmctrl1 clock to ramsn[1:0] and romsn[1:0]output delay 3) rising sdclk edge 0 1) 7.5 ns t ftmctrl1 clock to iosn output delay 3) rising sdclk edge 0 1) 8.5 ns t ftmctrl2 clock to output delay rising sdclk edge 0 1) 8.5 ns t ftmctrl3 clock to data output delay rising sdclk edge 0 1) 6.5 ns t ftmctrl4 clock to data non-tri-state delay rising sdclk edge 0 1) 6.5 ns t ftmctrl5 clock to data tri-state delay 4) rising sdclk edge 0 1) 6.5 1) ns t ftmctrl6 clock to output delay rising sdclk edge 0 1) 8.5 ns t ftmctrl7 data input to clock setup rising sdclk edge 6.9 - ns t ftmctrl8 data input from clock hold rising sdclk edge -0.5 1) - ns t ftmctrl9 input to clock setup rising sdclk edge 6.9 - ns t ftmctrl10 input from clock hold rising sdclk edge -0.5 1) - ns note 1: parameter not measured during production test. note 2: the speci?ed timing is valid for the default programmable internal clock delay of value 0. note 3: the address[23:0] and ramsn[1:0] signals change in the same clock cycle, which might not be compatible with all sram types. check your sram documentation for compatibility. note 4: GR712RC does not provide internal pull-up resistors on the data[31:0] and cb[15:0] buses. in the case of prolonged periods of idle bus activity in a board design, i.e. high impedance state, it is advised to add external pull-up resistors.
aeroflex gaisler 26 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 the timing waveforms and timing parameters are shown in ?gure 8 and are de?ned in table 15. the timing waveforms and timing parameters are shown in ?gure 9 and are de?ned in table 16. table 15. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge 2) min max unit t ftmctrl11 clock to output delay rising sdclk edge 1 1) 6 ns t ftmctrl12 clock to data output delay rising sdclk edge 1 1) 6.5 ns t ftmctrl13 data clock to data tri-state delay rising sdclk edge 1 1) 6.5 1) ns t ftmctrl14 data input to clock setup rising sdclk edge 6.9 - ns t ftmctrl15 data input from clock hold rising sdclk edge -0.5 1) - ns note 1: parameter not measured during production test. note 2: the speci?ed timing is valid for the default programmable internal clock delay of value 0. note 3: the maximum operating frequency of the GR712RC may be limited due to the timing performance of external sdram devices. table 16. timing parameters (v dd = 1.65 v, v ddio = 3.0 v, t case = +125?c) 1) name parameter reference min max unit t sdclk0 clock to output delay, delay value 0 rising inclk edge 7 10 ns t sdclk51 clock to output delay, delay value 51 rising inclk edge 16 25 ns note 1: production test performed at ?xed voltage and temperature. figure 8. timing waveforms - sdram accesses sdcasn, sdrasn sdclk sdwen, sdcsn[1:0] sddqm[3:0] write nop read nop nop term nop nop nop address[16:2] data[31:0], cb[15:0] t ftmctrl14 t ftmctrl11 t ftmctrl11 t ftmctrl13 t ftmctrl12 t ftmctrl15 figure 9. timing waveforms inclk t sdclk0, t sdclk51 sdclk
aeroflex gaisler 27 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.5 jtag debug interface the timing waveforms and timing parameters are shown in ?gure 10 and are de?ned in table 17. 2.4.6 general purpose timer unit the timing waveforms and timing parameters are shown in ?gure 11 and are de?ned in table 18. table 17. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t ahbjtag0 clock period - 100 - ns t ahbjtag1 clock low/high period - 40 - ns t ahbjtag2 data input to clock setup rising tck edge 10 1) - ns t ahbjtag3 data input from clock hold rising tck edge 10 1) - ns t ahbjtag4 clock to data output delay falling tck edge 0 1) 21 ns note 1: parameter not measured during production test. note 2: for correct operation, all jtag signals should be pulled-up externally with 1 - 10 kohm. this is in line with the tap speci?cation where tms and tdi implementation should be such that if an exter- nal signal fails (e.g. open circuit) then the behavior of tms and tdi should be equivalent to a logi- cal 1 input. GR712RC does not include any internal pull-up resistors. table 18. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t gptimer0 clock to output delay rising inclk edge 2 1) 23 2) ns t gptimer1 clock to output tri-state rising inclk edge 50 1) ns note 1: parameter not measured during production test. note 2: parameter measured during production test without dll enabled. note 3: for correct operation, the signal should be pulled-up externally with 1 - 10 kohm. GR712RC does not include any internal pull-up resistors. note 4: wdogn output is unde?ned during internal reset when dll is used to generate the internal system clock frequency. see section 2.4.2 for detailed timing information on the reset behavior. figure 10. timing waveforms tdi, tms tck tdo t ahbjtag3 t ahbjtag4 t ahbjtag2 t ahbjtag0 t ahbjtag1 figure 11. timing waveforms t gptimer0 wdogn inclk t gptimer1
aeroflex gaisler 28 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.7 general purpose input output port the timing waveforms and timing parameters are shown in ?gure 12 and are de?ned in table 19. 2.4.8 uart serial interface the timing waveforms and timing parameters are shown in ?gure 13 and are de?ned in table 20. table 19. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t grgpio0 clock to output delay rising inclk edge 2 1) 21 2) ns t grgpio1 clock to non-tri-state delay rising inclk edge 2 1) 21 1) ns t grgpio2 clock to tri-state delay rising inclk edge 50 1) ns t grgpio3 input to clock hold rising inclk edge - - ns 3) t grgpio4 input to clock setup rising inclk edge - - ns 3) note 1: parameter not measured during production test. note 2: parameter measured during production test without dll enabled. note 3: the gpio[...] inputs are re-synchronized to the internal system clock with a t clk period. table 20. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t apbuart0 clock to output delay rising inclk edge 2 1) 21 2) ns t apbuart1 input to clock hold rising inclk edge - - ns 3) t apbuart2 input to clock setup rising inclk edge - - ns 3) note 1: parameter not measured during production test. note 2: parameter measured during production test without dll enabled. note 3: the uart_rx[5:0] inputs are re-synchronized to the internal system clock with a t clk period. figure 12. timing waveforms t grgpio0 gpio[...] inclk t grgpio0 t grgpio1 gpio[...] t grgpio2 t grgpio3 gpio[...] t grgpio4 (output)(output) (input) figure 13. timing waveforms t apbuart0 uart_tx[5:0] inclk t apbuart0 t apbuart1 uart_rx[5:0] t apbuart2
aeroflex gaisler 29 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.9 spacewire interface the timing waveforms and timing parameters are shown in ?gure 14 and are de?ned in table 21. spwclk t spwclk spw_txd[5:0]spw_txs[5:0] t spw2 t spw2 t spw2 spw_txd[5:0] spw_txs[5:0] t spw3 figure 14. timing waveforms spw_rxd[5:0]spw_rxs[5:0] t spw4, t spw6 t spw4, t spw6 t spw4, t spw6 spw_rxd[5:0] spw_rxs[5:0] t spw5
aeroflex gaisler 30 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 table 21. timing parameters transmitter (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t spwclk input clock period without dll 5) spwclk 10 4) - ns f spwclk input clock frequency without dll 2) spwclk - 100 4) mhz dc spwclk input frequency duty cycle without dll 5) spwclk 45 55 % t spwclk input clock period with dll x2 1) 6) spwclk 20 22 4) ns f spwclk input clock frequency with dll x2 1) 2) spwclk 45 4) 50 mhz t spwclk input clock period with dll x4 1) 6) spwclk 20 22 4) ns f spwclk input clock frequency with dll x4 1) 2) spwclk 45 4) 50 mhz dc spwclk input frequency duty cycle with dll spwclk 35 4) 65 4) % t spw internal transmitter clock period 6) - 5 500 4) ns f spw internal transmitter clock frequency 2) 6) - 2 4) 200 mhz t spw2 output data bit period - 5 4) 500 4) ns t spw3 data & strobe output skew & jitter - - 500 4) ps t spw4 input data bit period - 5 4) 500 4) ns t spw5 data & strobe input skew, jitter & hold - - 800 4) ps t spw6 data & strobe edge separation 5) - 2500 4) - ps note 1: for the internal spacewire clock, the dll provides a times 2 or 4 multiplication of the input fre- quency. note 2: t spwclk = 1/f spwclk , t spw = 1/f spw note 3: n/a note 4: parameter not measured during production test. note 5: minimum internal edge separation equals half the internal transmitter clock period. minimum t spw6 is speci?ed at minimum t spw with 50% duty cycle. external edge separation should not be less than the sum of t spw5 + t spw6 . note 6: the maximum spacewire clock frequency is speci?ed by the parameters t spw and f spw . the parameters t spwclk and f spwclk specify the what the clock input pin and the dll can support, and not what the internal logic can support. note 7: the parameters t spw n are only valid between signals belonging to one spacewire link.
aeroflex gaisler 31 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.10 ethernet media access controller (mac) the timing waveforms and timing parameters are shown in ?gure 15 and are de?ned in table 22. 2.4.11 can interface the timing waveforms and timing parameters are shown in ?gure 16 and are de?ned in table 23. table 22. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t grethref ethernet reference clock period any rmrfclk edge 20 4) - ns t greth0 transmitter clock to output delay rising rmrfclk edge 2 1) 15 ns t greth1 input to receiver clock hold rising rmrfclk edge 2 - ns t greth2 input to receiver clock setup rising rmrfclk edge 4 - ns note 1: parameter not measured during production test. note 2: the rmintn, rmmdio and rmcrsdv inputs are re-synchronized internally. note 3: the rmmdio and rmmdc outputs are low speed signals without any timing relationship with the rmrfclk clock. note 4: according to ethernet standard the reference clock rmrfclk frequency must be 50 mhz +/- 50 ppm. table 23. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t can_oc0 clock to data output delay rising inclk edge 2 1) 21 1) ns t can_oc1 data input to clock setup rising inclk edge - - ns 3) t can_oc2 data input from clock hold rising inclk edge - - ns 3) note 1: parameter not measured during production test. note 2: parameter measured during production test without dll enabled. note 3: the canrx[a:b] input is re-synchronized to the internal system clock with a t clk period. figure 15. timing waveforms t greth0 rmtxd[1:0], rmtxen rmrfclk t greth0 t greth1 t greth2 rmrxd[1:0] figure 16. timing waveforms t can_oc0 cantx[a:b] inclk canrx[a:b] t can_oc2 t can_oc1
aeroflex gaisler 32 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.12 obsolete proprietary function not supported. 2.4.13 mil-std-1553b bc/rt/bm the timing waveforms and timing parameters are shown in ?gure 17 and are de?ned in table 24. table 24. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t 1553brm0 clock to data output delay rising 1553ck edge 2 1) 21 1) ns t 1553brm1 data input to clock setup rising 1553ck edge - - ns 2) t 1553brm2 data input from clock hold rising 1553ck edge - - ns 2) t 1553brm3 clock frequency 1553ck 16, 20, 24 mhz 3) note 1: parameter not measured during production test. note 2: the 1553rxa, 1553rxan, 1553rxb and 1553rxbn inputs are re-synchronized internally. note 3: the core frequency must be lower than the internal system frequency: t 1553brm3 < f clk figure 17. timing waveforms t 1553brm0 1553txa/txan 1553ck 1553rxa/rxan t 1553brm2 t 1553brm1 1553rxb/rxbn 1553txb/txbn1553txinha, 1553txinhb 1553rxena, 1553rxenb
aeroflex gaisler 33 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.14 i2c-master the timing waveforms and timing parameters are shown in ?gure 18 and are de?ned in table 25. table 25. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t i2c0 data output valid before clock rising i2cscl edge - scaler 1) t clk periods t i2c1 data output valid after clock falling i2cscl edge scaler 1) - t clk periods t i2c2 data input setup to clock rising i2cscl edge 2 2) - t clk periods t i2c3 data input hold from clock falling i2cscl edge 0 2) - t clk periods note 1: the cores i2c bus functional timing depends on the cores scaler value and the internal system clock t clk period. when the scaler is set for the core to operate in fast- or standard-mode, the timing charac- teristics in the i2c-bus speci?cation apply. the maximum t clk period for proper operation is 50 ns. note 2: the i2cscl and i2csda inputs are re-synchronized to the internal system clock with a t clk period. note 3: i2cscl and i2csda are open-drain outputs, driving a logical 0 level or tri-state. note 4: for correct operation, the signals should be pulled-up externally with 10 kohm. GR712RC does not include any internal pull-up resistors. figure 18. timing waveforms t i2c0 i2csda i2cscl i2csda t i2c3 t i2c2 t i2c1 (output)(input) (input/output)
aeroflex gaisler 34 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.15 spi controller the timing waveforms and timing parameters are shown in ?gure 19 and are de?ned in table 26. 2.4.16 slink serial bus based real-time network master the timing waveforms and timing parameters are shown in ?gure 20 and are de?ned in table 27. table 26. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t spictrl0 clock to output delay driving spiclk edge -15 2) 15 2) ns 1) t spictrl1 input to clock hold sampling spiclk edge 0 2) - ns 3) t spictrl2 input to clock setup sampling spiclk edge 20 2) - ns 3) note 1: the driving and sampling edges of the interface are programmable, and always opposite to each other. note 2: parameter not measured during production test. note 3: the spimiso input is re-synchronized to the internal system clock with a t clk period. table 27. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t slink0 clock to output delay rising slclk edge 1 - t clk periods 1) t slink1 input to clock hold rising slclk edge 0 - t clk periods t slink2 input to clock setup rising slclk edge 2 - t clk periods note 1: output timing depends on the odel setting in the cores control register. outputs will transition (odel+1)*(system clock period) ns after slclk rising edge. figure 19. timing waveforms t spictrl0 spimosi spiclk t spictrl0 t spictrl1 spimiso t spictrl2 figure 20. timing waveforms t slink0 slo, slsync slclk t slink0 t slink1 sli t slink2 (output)(input)
aeroflex gaisler 35 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.17 ascs controller the timing waveforms and timing parameters are shown in ?gure 21 and are de?ned in table 28. table 28. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t ascs0 clock period rising a16hs edge 2 - t clk periods 1) t ascs1 quali?er de-asserted width - 20 - t clk periods 1) t ascs2 quali?er asserted to clock rising a16hs edge 8 - t clk periods 1) t ascs3 clock to quali?er de-asserted falling a16hs edge 2 - t clk periods 1) t ascs4 output data to clock setup rising a16hs edge 1 - t clk periods 1) t ascs5 output data after clock hold rising a16hs edge 1 - t clk periods 1) t ascs6 input data to clock setup rising a16hs edge 2 - t clk periods t ascs7 input data after clock hold rising a16hs edge 2 - t clk periods note 1: the timing of the interface is programmable and is dependable on the t ascs0 clock period. figure 21. timing waveforms t ascs0 a16mcs, a16mas t ascs1 t ascs2 a16dcs a16hs a16dasa, a16dasb t ascs3 t ascs4 t ascs5 t ascs7 t ascs6
aeroflex gaisler 36 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 2.4.18 ccsds / ecss telecommand decoder the timing waveforms and timing parameters are shown in ?gure 22 and are de?ned in table 29. 2.4.19 ccsds / ecss telemetry encoder the timing waveforms and timing parameters are shown in ?gure 23 and are de?ned in table 30. table 29. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t grtc0 bit period rising tcclk edge 7 - t clk periods t grtc1 data/active input to clock hold rising tcclk edge 3 - t clk periods t grtc2 data/active input to clock setup rising tcclk edge 3 - t clk periods t grtc3 rf available input to clock hold rising inclk edge - - ns 1) t grtc4 rf available input to clock setup rising inclk edge - - ns 1) note 1: the tcrfavl[4:0] inputs are re-synchronized to the internal system clock with a t clk period. table 30. timing parameters (v dd = 1.8 v +/- 0.15 v, v ddio = 3.3 v +/- 0.3 v, t case = -55?c to +125?c) name parameter reference edge min max unit t grtm0 clock to output delay any tmclko edge -15 3) 15 3) ns 1) t grtm1 input to clock hold rising inclk edge - - ns 2) t grtm2 input to clock setup rising inclk edge - - ns 2) t grtm3 input to output delay tmclki to tmclko 0 3) 23 3) ns t grtm4 tmclki clock period - 20 3) ns note 1: the tmdo signal is output simultaneously with the programmable tmclko clock edge. the oppo- site clock edge should be used for sampling tmdo. note 2: the tcact[4:0] and tcrfavl[4:0] inputs are re-synchronized to the t clk period. note 3: parameter not measured during production test. figure 22. timing waveforms tcclk[4:0] t grtc1 tcact[4:0] t grtc2 tcd[4:0] tcrfavl[4:0] t grtc3 t grtc4 t grtc0 figure 23. timing waveforms t grtm0 tmdo tmclko t grtm0 t grtm1 tcact[4:0], tcrfavl[4:0] t grtm2
aeroflex gaisler 37 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 3 mechanical description 3.1 package ceramic hermetically sealed cqfp-240l package with 0.5 mm lead pitch, with gold plated leads. see drawing in section 3.3. all devices are marked on top lid with GR712RC. for space class marking see the product speci?ca- tion [ps]. lead trimming and forming are performed by customer prior to assembly on printed circuit board. 3.2 pin assignment the pin assignment in table 31 shows the implementation characteristics of each signal, indicating how each pin has been con?gured in terms of maximum load, polarity and reset value. table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note 1 swmx[3] in - i/o switch matrix 3 2 swmx[2] out 50 - high i/o switch matrix 2 3 swmx[1] in - i/o switch matrix 1 4 swmx[0] out 50 - high i/o switch matrix 0 5 cb[6] in/out 50 - high-z check bit 6 6 vddio i/o supply voltage 7 gndio 2) i/o supply ground 8 cb[5] in/out 50 - high-z check bit 5 9 cb[4] in/out 50 - high-z check bit 4 10 cb[3] in/out 50 - high-z check bit 3 11 cb[2] in/out 50 - high-z check bit 2 12 cb[1] in/out 50 - high-z check bit 1 13 vdd core supply voltage 14 gnd core supply ground 15 cb[0] in/out 50 - high-z check bit 0 16 data[31] in/out 50 - high-z data bit 31 17 data[30] in/out 50 - high-z data bit 30 18 vddio i/o supply voltage 19 gndio i/o supply ground 20 data[29] in/out 50 - high-z data bit 29 21 data[28] in/out 50 - high-z data bit 28 22 data[27] in/out 50 - high-z data bit 27 23 data[26] in/out 50 - high-z data bit 26 24 data[25] in/out 50 - high-z data bit 25 25 data[24] in/out 50 - high-z data bit 24 26 data[23] in/out 50 - high-z data bit 23 27 data[22] in/out 50 - high-z data bit 22 28 vddio i/o supply voltage 29 gndio i/o supply ground 30 vdd core supply voltage 31 gnd core supply ground
aeroflex gaisler 38 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 32 data[21] in/out 50 - high-z data bit 21 33 data[20] in/out 50 - high-z data bit 20 34 data[19] in/out 50 - high-z data bit 19 35 data[18] in/out 50 - high-z data bit 18 36 data[17] in/out 50 - high-z data bit 17 37 data[16] in/out 50 - high-z data bit 16 38 vddio i/o supply voltage 39 gndio i/o supply ground 40 data[15] in/out 50 - high-z data bit 15 41 data[14] in/out 50 - high-z data bit 14 42 data[13] in/out 50 - high-z data bit 13 43 data[12] in/out 50 - high-z data bit 12 44 data[11] in/out 50 - high-z data bit 11 45 data[10] in/out 50 - high-z data bit 10 46 data[9] in/out 50 - high-z data bit 9 47 vdd core supply voltage 48 gnd core supply ground 49 data[8] in/out 50 - high-z data bit 8 50 vddio i/o supply voltage 51 gndio i/o supply ground 52 data[7] in/out 50 - high-z data bit 7 53 data[6] in/out 50 - high-z data bit 6 54 data[5] in/out 50 - high-z data bit 5 55 data[4] in/out 50 - high-z data bit 4 56 data[3] in/out 50 - high-z data bit 3 57 data[2] in/out 50 - high-z data bit 2 58 data[1] in/out 50 - high-z data bit 1 59 data[0] in/out 50 - high-z data bit 0 60 vddio i/o supply voltage 61 gndio i/o supply ground 62 address[0] out 50 - low address bit 0 63 address[1] out 50 - low address bit 1 64 address[2] out 100 - low address bit 2 65 address[3] out 100 - low address bit 3 66 vdd core supply voltage 67 gnd core supply ground 68 address[4] out 100 - low address bit 4 69 vddio i/o supply voltage 70 gndio i/o supply ground 71 address[5] out 100 - low address bit 5 72 address[6] out 100 - low address bit 6 73 address[7] out 100 - low address bit 7 74 address[8] out 100 - low address bit 8 75 vddio i/o supply voltage 76 gndio i/o supply ground 77 address[9] out 100 - low address bit 9 78 vdd core supply voltage table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note
aeroflex gaisler 39 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 79 gnd core supply ground 80 address[10] out 100 - low address bit 10 81 address[11] out 100 - low address bit 11 82 address[12] out 100 - low address bit 12 83 vddio i/o supply voltage 84 gndio i/o supply ground 85 address[23] out 50 - low address bit 23 86 address[13] out 100 - low address bit 13 87 address[22] out 50 - low address bit 22 88 address[21] out 50 - low address bit 21 89 address[14] out 100 - low address bit 14 90 vdd core supply voltage 91 gnd core supply ground 92 address[20] out 50 - low address bit 20 93 vddio i/o supply voltage 94 gndio i/o supply ground 95 address[19] out 50 - low address bit 19 96 address[15] out 100 - low address bit 15 97 address[18] out 50 - low address bit 18 98 address[16] out 100 - low address bit 16 99 address[17] out 50 - low address bit 17 100 scanen in high scan enable (tie to ground) 101 romsn[0] out 50 low high prom select 0 102 vdd core supply voltage 103 gnd core supply ground 104 vddio i/o supply voltage 105 gndio i/o supply ground 106 romsn[1] out 50 low high prom select 1 107 writen out 50 low high write strobe for prom, i/o 108 iosn out 50 low high i/o select 109 ramsn[0] out 50 low high sram select 0 110 ramsn[1] out 50 low high sram select 1 111 ramoen out 50 low high sram output enable 112 ramwen out 50 low high sram write enable 113 brdyn in low bus ready 114 vdd core supply voltage 115 gnd core supply ground 116 vddio i/o supply voltage 117 gndio i/o supply ground 118 bexcn in low bus exception 119 wdogn out 50 low high-z watchdog indicator (output is driven active low, else it is in tri-state and therefore requires external pull-up) 120 read out 50 high high sram, prom, i/o read indicator 121 tdi in - jtag test data in 122 tck in - jtag test clock 123 tms in high jtag test mode select 124 tdo out 50 - low jtag test data out table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note
aeroflex gaisler 40 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 125 testen in high test enable (tie to ground) 126 oen out low high output enable for prom, i/o 127 swmx[66] in/out 50 - high-z i/o switch matrix 66 128 swmx[65] in/out 50 - high-z i/o switch matrix 65 129 swmx[64] in/out 50 - high-z i/o switch matrix 64 130 vddio i/o supply voltage 131 gndio i/o supply ground 132 swmx[63] in/out 50 - high-z i/o switch matrix 63 133 vdd core supply voltage 134 gnd core supply ground 135 swmx[62] in/out 50 - high-z i/o switch matrix 62 136 swmx[61] in/out 50 - high-z i/o switch matrix 61 137 swmx[60] in/out 50 - high-z i/o switch matrix 60 138 vddio i/o supply voltage 139 gndio i/o supply ground 140 swmx[59] in/out 50 - high-z i/o switch matrix 59 141 cb[7] in/out 50 - high-z check bit 7 142 swmx[58] in/out 50 - high-z i/o switch matrix 58 143 swmx[57] in/out 50 - high-z i/o switch matrix 57 144 swmx[56] in - i/o switch matrix 56 145 resetn in low system reset 146 errorn out 50 low high-z processor error mode (output is driven active low, else it is in tri-state and therefore requires external pull-up) 147 dllbpn in low dll bypass 148 inclk in - input clock 149 vddio i/o supply voltage 150 vdd core supply voltage 151 gnd core supply ground 152 gndio i/o supply ground 153 swmx[55] in - i/o switch matrix 55 154 swmx[54] in/out 100 - high-z i/o switch matrix 54 155 swmx[53] in/out 100 - high-z i/o switch matrix 53 156 sdclk out 100 - - sdram clock 157 swmx[52] in/out 100 - high-z i/o switch matrix 52 158 vddio i/o supply voltage 159 gndio i/o supply ground 160 swmx[51] in - i/o switch matrix 51 161 swmx[50] in - i/o switch matrix 50 162 swmx[49] in/out 100 - high-z i/o switch matrix 49 163 swmx[48] in/out 100 - high-z i/o switch matrix 48 164 swmx[47] in - i/o switch matrix 47 165 swmx[46] in - i/o switch matrix 46 166 swmx[45] in/out 50 - high-z i/o switch matrix 45 1) 167 vdd core supply voltage 168 gnd core supply ground 169 swmx[44] in/out 50 - high-z i/o switch matrix 44 170 vddio i/o supply voltage table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note
aeroflex gaisler 41 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 171 gndio i/o supply ground 172 swmx[43] in/out 50 - high-z i/o switch matrix 43 1) 173 swmx[42] in - i/o switch matrix 42 174 swmx[41] in/out 50 - high-z i/o switch matrix 41 175 swmx[40] in/out 50 - high-z i/o switch matrix 40 1) 176 swmx[39] in - i/o switch matrix 39 177 swmx[38] in - i/o switch matrix 38 178 swmx[37] in/out 50 - high-z i/o switch matrix 37 1) 179 swmx[36] in/out 50 - high-z i/o switch matrix 36 180 vddio i/o supply voltage 181 gndio i/o supply ground 182 swmx[35] in - i/o switch matrix 35 183 swmx[34] in - i/o switch matrix 34 184 swmx[33] in/out 50 - high-z i/o switch matrix 33 185 swmx[32] in/out 50 - high-z i/o switch matrix 32 186 vdd core supply voltage 187 gnd core supply ground 188 swmx[31] in - i/o switch matrix 31 189 swmx[30] in - i/o switch matrix 30 190 swmx[29] in/out 50 - high-z i/o switch matrix 29 191 swmx[28] in/out 50 - high-z i/o switch matrix 28 192 swmx[27] in - i/o switch matrix 27 193 swmx[26] in - i/o switch matrix 26 194 vddio i/o supply voltage 195 gndio i/o supply ground 196 swmx[25] in/out 100 - high-z i/o switch matrix 25 197 swmx[24] in/out 100 - high-z i/o switch matrix 24 198 vdd core supply voltage 199 gnd core supply ground 200 swmx[23] in - i/o switch matrix 23 201 swmx[22] in - i/o switch matrix 22 202 swmx[21] in/out 100 - high-z i/o switch matrix 21 203 swmx[20] in/out 100 - high-z i/o switch matrix 20 204 spw_rxd[1] - spacewire receive data 1 205 spw_rxs[1] - spacewire receive strobe 1 206 spw_txd[1] out 100 - low spacewire transmit data 1 207 vddio i/o supply voltage 208 gndio i/o supply ground 209 spw_txs[1] out 100 - low spacewire transmit strobe 1 210 vdd core supply voltage 211 gnd core supply ground 212 spwclk in - spacewire receiver and transmitter clock 213 spw_rxd[0] in - spacewire receive data 0 214 spw_rxs[0] in - spacewire receive strobe 0 215 spw_txd[0] out 100 - low spacewire transmit data 0 216 spw_txs[0] out 100 - low spacewire transmit strobe 0 217 swmx[19] in 50 - i/o switch matrix 19 table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note
aeroflex gaisler 42 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 218 swmx[18] in - i/o switch matrix 18 219 swmx[17] in/out 100 - high-z i/o switch matrix 17 220 swmx[16] in/out 100 - high-z i/o switch matrix 16 221 vddio i/o supply voltage 222 vdd core supply voltage 223 gnd core supply ground 224 gndio i/o supply ground 225 swmx[15] in - i/o switch matrix 15 226 swmx[14] in - i/o switch matrix 14 227 swmx[13] in/out 100 - high-z i/o switch matrix 13 228 swmx[12] in/out 100 - high-z i/o switch matrix 12 229 swmx[11] in - i/o switch matrix 11 230 swmx[10] in/out 50 - high-z i/o switch matrix 10 231 swmx[9] in - i/o switch matrix 09 232 swmx[8] in/out 50 - high-z i/o switch matrix 08 233 swmx[7] in - i/o switch matrix 07 234 vdd core supply voltage 235 gnd core supply ground 236 vddio i/o supply voltage 237 gndio i/o supply ground 238 swmx[6] in/out 50 - high-z i/o switch matrix 06 1) 239 swmx[5] in - i/o switch matrix 05 240 swmx[4] in/out 50 - high-z i/o switch matrix 04 1) note 1: see tables 3 and 5 for detailed description of behavior at reset. note 2: gndio is connected internally to gnd. table 31. pin assignment pin no. pin name dir. max load [pf] polarity reset value note
aeroflex gaisler 43 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 3.3 mechanical package drawings table 32. dimensions millimeters min. max. a total height --- 3.50 a1 body height --- 2.75 a2 0.10 0.40 b lead width 0.15 0.25 c lead height 0.10 0.20 d/e 74.80 75.40 d1/e1 55.44 56.56 d2/e2 31.75 32.25 d3/e3 29.50 bsc d4/e4 21.00 typ e lead pitch 0.50 bsc l1 16.50 typ note 1: the seal ring is electrically connected to gnd. note 2: package weight is 16 1 grams, including the lead-frame. figure 24. top view gndgnd v dd v ddio gndgnd v dd v ddio
aeroflex gaisler 44 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 figure 25. capacitor pads on top of package (mm)
aeroflex gaisler 45 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 4 reference documents [um] GR712RC dual-core leon3-ft sparc v8 processor - user's manual, aero?ex gaisler, www.aero?ex.com/gaisler [ps] product speci?cation GR712RC, GR712RC-ps, aero?ex gaisler [sparc] the sparc architecture manual, version 8, revision sav080si9308, sparc international inc. [spw] ecss - space engineering, spacewire - links, nodes, routers and networks, ecss-e-st-50-12c, 31 july 2008 [rmapid] ecss - space engineering, spacewire protocol identi?cation, ecss-e-st-50-51c, february 2010 [rmap] ecss - space engineering, remote memory access protocol, ecss-e-st-50-52c, february 2010 [ 1553brm ] core1553brm product handbook, 50200040-0/11-04, november 2004, actel corpo- ration core1553brm mil-std-1553 bc, rt, and mt, 51700052-4/12.05, v 5.0, december 2005, actel corporation core1553brm user's guide, 50200023-0/06.04, june 2004, actel corporation core1553brm v2.16 release notes, 51300019-8/6.06, june 2006, actel corporation [mil883] test method standard, microcircuits, revision h, 26 february 2010, mil-std-883h [mil38535] integrated circuits (microcircuits) manufacturing, general speci?cation for, revision j, 28 december 2010, mil-prf-38535j
aeroflex gaisler 46 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 5 screening, quali?cation, and quality control GR712RC is provided as a high reliability product for space, for which space level screening and quali?cations tests are performed in accordance to the product speci?cation [ps]. a certi?cate of compliance is delivered with space grade parts. a procurement speci?cation is provided for space grade parts. GR712RC is also provided in prototype grade in military or commercial temperature range. 6 ordering information ordering information is provided in table 33 and a legend is provided in table 34. table 33. ordering information, available models product description GR712RC-ms-cg240 flight model GR712RC-mp-cg240 electrical quali?cation model GR712RC-cp-cg240 engineering model (prototype) table 34. ordering legend designator option description product GR712RC dual-core leon3-ft sparc v8 processor temperature range m -55?c to +125?c (military range) i -40?c to +85?c (industrial range) c 0?c to +70?c (commercial range) screening level s space grade p prototype grade package type c ceramic quad flat pack (cqfp) lead finish g gold lead count 240 number of leads
aeroflex gaisler 47 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 7 change record change record information is provided in table 35. table 35. change record issue date sections note 2.0 2013 february 1.2 1.42.1 2.2 2.3 2.4 2.4.1, 2.4.3, 2.4.4, 2.4.5, 2.4.6, 2.4.7, 2.4.8, 2.4.9, 2.4.10, 2.4.11, 2.4.13, 2.4.15, 2.4.19 1.5, 2.4.12 3.1 3.2 3.3 4 key features updated signal descriptions clari?ed absolute maximum ratings updated recommended operating conditions updated dc parameters updated ac parameter test conditions clari?ed updated timing obsolete proprietary function removed package marking clari?ed gndio connection to gnd clari?ed weight information added reference to product speci?cation added 1.5 2012 may 1.5 the following con?icts added to table: ccsds tc 0 vs. proprietaryccsds tc 0 vs. ascs ccsds tc 1 vs. proprietary ccsds tc 1 vs. ethernet ccsds tc 2 vs. ethernet proprietary vs. spacewire 2 1.4 2012 january 2.4.5 tck edges in jtag waveform & timing parameters corrected 1.3 2011 march 1.2, 2 4, 5 table 6 timing parameters rede?ned quali?cation level speci?ed con?ict between slink and ccsds tc 3 clari?ed 1.2 2011 august 2.3 added detailed core power consumption 1.1 2011 february tables 3 and 5 tables 3, 4 and 19, ?gure 19 table 31 sddqm signals marked as active high gpio1/gpio2 names changed to gpio reference added regarding behavior at reset 1.0 2011 february all new document layout all pin descriptions, reset values etc. updated
aero?ex gaisler ab tel +46 31 7758650 kungsgatan 12 fax +46 31 421407 411 19 g?teborg sales@gaisler.com sweden www.aero?ex.com/gaisler copyright ? 2013 aero?ex gaisler ab. all information is provided as is. there is no warranty that it is correct or suitable for any purpose, neither implicit nor explicit. information furnished by aero?ex gaisler ab is believed to be accurate and reliable. however, no responsibility is assumed by aero?ex gaisler ab for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of aero?ex gaisler ab. aeroflex gaisler 48 GR712RC-ds copyright aero?ex gaisler ab february 2013, issue 2.0 gaisler

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